# Symbol definition of ADS5521 ADC (TI) for gschem/gEDA
# S. Salewski, 28-JUL-2007
# File: ADS5521.txt
# The Python script "tragesym" is used to convert this textual symbol definition to a symbol
# usage: tragesym ADS5521.txt ADS5521.sym
# This will result in a large symbol with 64 pins --
# division in multiple subsymbols (power, digital, analog) with gschem is useful

# tragesym options

[options]
# wordswap swaps labels if the pin is on the right side and looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=no
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=1400
pinwidthvertical=300
pinwidthhorizontal=400

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=ADS5521
device=ADS5521
refdes=U?
footprint=TQFP64_14
description=ADC from TI, 12-bit, upto 105MSPS
documentation=http://focus.ti.com/docs/prod/folders/print/ads5521.html
author=Stefan Salewski
#dist-license and use-license are supported by tragesym 0.11 and newer
dist-license=GPL
use-license=unlimited
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=dist-license=GPL
#comment=use-license=unlimited
comment=generated with Python script tragesym

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	
#-----------------------------------------------------
#pinnr	seq	type	style	posit	net 	label	comment
# Power supply, ground, misc
5		pwr	line	l		AVDD	Analog power supply
7		pwr	line	l		AVDD	Analog power supply
9		pwr	line	l		AVDD	Analog power supply
15		pwr	line	l		AVDD	Analog power supply
22		pwr	line	l		AVDD	Analog power supply
24		pwr	line	l		AVDD	Analog power supply
26		pwr	line	l		AVDD	Analog power supply
28		pwr	line	l		AVDD	Analog power supply
33		pwr	line	l		AVDD	Analog power supply
34		pwr	line	l		AVDD	Analog power supply
37		pwr	line	l		AVDD	Analog power supply
39		pwr	line	l		AVDD	Analog power supply

6		pwr	line	r		AGND	Analog ground
8		pwr	line	r		AGND	Analog ground
12		pwr	line	r		AGND	Analog ground
13		pwr	line	r		AGND	Analog ground
14		pwr	line	r		AGND	Analog ground
16		pwr	line	r		AGND	Analog ground
18		pwr	line	r		AGND	Analog ground
21		pwr	line	r		AGND	Analog ground
23		pwr	line	r		AGND	Analog ground
25		pwr	line	r		AGND	Analog ground
27		pwr	line	r		AGND	Analog ground
32		pwr	line	r		AGND	Analog ground
36		pwr	line	r		AGND	Analog ground
38		pwr	line	r		AGND	Analog ground

49		pwr	line	l		DRVDD	Output driver power supply
58		pwr	line	l		DRVDD	Output driver power supply

1		pwr	line	r		DRGND	Output driver ground
42		pwr	line	r		DRGND	Output driver ground
48		pwr	line	r		DRGND	Output driver ground
50		pwr	line	r		DRGND	Output driver ground
57		pwr	line	r		DRGND	Output driver ground
59		pwr	line	r		DRGND	Output driver ground

44		pas	line	l		NC	Not connected
45		pas	line	l		NC	Not connected

29		out	line	l		REFP	Reference voltage (positive); 1-µF capacitor in series with a 1-Ω resistor to GND
30		out	line	l		REFM	Reference voltage (negative); 1-µF capacitor in series with a 1-Ω resistor to GND
31		in	line	l		IREF	Current set; 56-kΩ resistor to GND; do not connect capacitors

# Analog input and common-mode output voltage
17		out	line	l		CM	Common-mode output voltage
19		in	line	l		INP	Differential analog input (positive)
20		in	line	l		INM	Differential analog input (negative)

# Clock input
10		clk	clk	l		CLKP	Data converter differential input clock (positive)
11		clk	clk	l		CLKM	Data converter differential input clock (negative)

# Control interface
2		in	line	l		SCLK	Serial interface clock
3		in	line	l		SDATA	Serial interface data 
4		in	line	l		SEN	Serial interface chip select
35		in	line	l		RESET	Reset (active high), 200-kΩ resistor to AVDD
41		in	line	l		OE	Output enable (active high)
40		in	line	l		DFS	Data format and clock out polarity select

# Digital output
43		clk	clk	l		CLKOUT	CMOS clock out in sync with data
46		out	line	l		D0	Parallel data output (LSB)
47		out	line	l		D1	Parallel data output
51		out	line	l		D2	Parallel data output
52		out	line	l		D3	Parallel data output
53		out	line	l		D4	Parallel data output
54		out	line	l		D5	Parallel data output
55		out	line	l		D6	Parallel data output
56		out	line	l		D7	Parallel data output
60		out	line	l		D8	Parallel data output
61		out	line	l		D9	Parallel data output
62		out	line	l		D10	Parallel data output
63		out	line	l		D11	Parallel data output (MSB)
64		out	line	l		OVR	Over-range indicator bit
