# Symbol definition of CY7C1380D (100-pin TQFP) for gschem/gEDA
# S. Salewski, 18-MAY-2008
# File: CY7C1380D-1.txt
# The Python script "tragesym" is used to convert this textual symbol definition to a symbol
# usage: CY7C1380D-1.txt CY7C1380D-1.sym

# tragesym options

[options]
# wordswap swaps labels if the pin is on the right side and looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=no
rotate_labels=yes
sort_labels=no
generate_pinseq=yes
sym_width=7200
pinwidthvertical=300
pinwidthhorizontal=300

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113
name=CY7C1380D
device=CY7C1380D
refdes=U?
footprint=TQFP-65P-1600L1-2200L2-100N
description=18-Mbit (512K x 36) Pipelined SRAM
documentation=http://www.cypress.com/products/?fid=39&rpn=CY7C1380D&ref=sch
author=Stefan Salewski
dist-license=GPL
use-license=unlimited
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
comment=generated with Python script tragesym

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	
#-----------------------------------------------------
1		io	line	l		DQPC
2		io	line	l		DQC
3		io	line	l		DQC
4		pwr	line	l		VDDQ
5		pwr	line	l		VSSQ
6		io	line	l		DQC
7		io	line	l		DQC
8		io	line	l		DQC
9		io	line	l		DQC
10		pwr	line	l		VSSQ
11		pwr	line	l		VDDQ
12		io	line	l		DQC
13		io	line	l		DQC
14		pas	line	l		NC
15		pwr	line	l		VDD
16		pas	line	l		NC
17		pwr	line	l		VSS
18		io	line	l		DQD
19		io	line	l		DQD
20		pwr	line	l		VDDQ
21		pwr	line	l		VSSQ
22		io	line	l		DQD
23		io	line	l		DQD
24		io	line	l		DQD
25		io	line	l		DQD
26		pwr	line	l		VSSQ
27		pwr	line	l		VDDQ
28		io	line	l		DQD
29		io	line	l		DQD
30		io	line	l		DQPD
31		in	line	b		MODE
32		in	line	b		A
33		in	line	b		A
34		in	line	b		A
35		in	line	b		A
36		in	line	b		A1
37		in	line	b		A0
38		in	line	b		NC/72M
39		in	line	b		NC/36M
40		pwr	line	b		VSS
41		pwr	line	b		VDD
42		in	line	b		A
43		in	line	b		A
44		in	line	b		A
45		in	line	b		A
46		in	line	b		A
47		in	line	b		A
48		in	line	b		A
49		in	line	b		A
50		in	line	b		A
80		io	line	r		DQPB
79		io	line	r		DQB
78		io	line	r		DQB
77		pwr	line	r		VDDQ
76		pwr	line	r		VSSQ
75		io	line	r		DQB
74		io	line	r		DQB
73		io	line	r		DQB
72		io	line	r		DQB
71		pwr	line	r		VSSQ
70		pwr	line	r		VDDQ
69		io	line	r		DQB
68		io	line	r		DQB
67		pwr	line	r		VSS
66		pas	line	r		NC
65		pwr	line	r		VDD
64		in	line	r		ZZ
63		io	line	r		DQA
62		io	line	r		DQA
61		pwr	line	r		VDDQ
60		pwr	line	r		VSSQ
59		io	line	r		DQA
58		io	line	r		DQA
57		io	line	r		DQA
56		io	line	r		DQA
55		pwr	line	r		VSSQ
54		pwr	line	r		VDDQ
53		io	line	r		DQA
52		io	line	r		DQA
51		io	line	r		DQPA
100		in	line	t		A
99		in	line	t		A
98		in	line	t		\_CE1
97		in	line	t		CE2
96		in	line	t		\_BWD
95		in	line	t		\_BWC
94		in	line	t		\_BWB
93		in	line	t		\_BWA
92		in	line	t		\_CE3
91		pwr	line	t		VDD
90		pwr	line	t		VSS
89		clk	line	t		CLK
88		in	line	t		\_GW
87		in	line	t		\_BWE
86		in	line	t		\_OE
85		in	line	t		\_ADSC
84		in	line	t		\_ADSP
83		in	line	t		\_ADV
82		in	line	t		A
81		in	line	t		A

