# Symbol definition of Spartan-3E FPGA for gschem/gEDA
# Bank 1 (_1 deleted in pinlabel)
# S. Salewski, 26-OCT-2007
# File: XC3S500E-PQ208-B1.txt (based on file pq208_pinout.csv available from Xilinx)
# The Python script "tragesym" is used to convert this textual symbol definition into a symbol
# usage: tragesym XC3S500E-PQ208-B1.txt XC3S500E-PQ208-B1.sym

# tragesym options

[options]
# wordswap swaps labels if the pin is on the right side and looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=no
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=2400
pinwidthvertical=200
pinwidthhorizontal=400

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=XC3S500E-PQ208
device=XC3S500E-PQ208
refdes=U?
footprint=QFP208_28
description=FPGA
documentation=http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf
author=Stefan Salewski
dist-license=GPL
use-license=unlimited
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
comment=generated with Python script tragesym

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	comment
#-----------------------------------------------------
#pinnr	seq	type	style	posit	net 	label	type	bank		
#
106		io	line	l		IO_L01P/A16	DUAL	1
107		io	line	l		IO_L01N/A15	DUAL	1
108		io	line	l		IO_L02P/A14	DUAL	1
109		io	line	l		IO_L02N/A13	DUAL	1
110		in	line	l		IP	INPUT	1
112		io	line	l		IO_L03P	I/O	1
113		io	line	l		IO_L03N/VREF	VREF	1
115		io	line	l		IO_L04P	I/O	1
116		io	line	l		IO_L04N	I/O	1
118		in	line	l		IP	INPUT	1
119		io	line	l		IO_L05P/A12	DUAL	1
120		io	line	l		IO_L05N/A11	DUAL	1
122		io	line	l		IO_L06P	I/O	1
123		io	line	l		IO_L06N/VREF	VREF	1
124		in	line	l		IP	INPUT	1
126		io	line	l		IO_L07P/A10/RHCLK0	RHCLK/DUAL	1
127		io	line	l		IO_L07N/A9/RHCLK1	RHCLK/DUAL	1
128		io	line	l		IO_L08P/A8/RHCLK2	RHCLK/DUAL	1
129		io	line	l		IO_L08N/A7/RHCLK3/TRDY1	RHCLK/DUAL	1
130		in	line	l		IP	INPUT	1
132		io	line	l		IO_L09P/A6/RHCLK4/IRDY1	RHCLK/DUAL	1
133		io	line	l		IO_L09N/A5/RHCLK5	RHCLK/DUAL	1
134		io	line	l		IO_L10P/A4/RHCLK6	RHCLK/DUAL	1
135		io	line	l		IO_L10N/A3/RHCLK7	RHCLK/DUAL	1
136		in	line	l		IP/VREF	VREF	1
137		io	line	l		IO_L11P/A2	DUAL	1
138		io	line	l		IO_L11N/A1	DUAL	1
139		io	line	l		IO_L12P	I/O	1
140		io	line	l		IO_L12N/A0	DUAL	1
142		in	line	l		IP	INPUT	1
144		io	line	l		IO_L13P	I/O	1
145		io	line	l		IO_L13N	I/O	1
146		io	line	l		IO_L14P	I/O	1
147		io	line	l		IO_L14N	I/O	1
148		in	line	l		IP	INPUT	1
150		io	line	l		IO_L15P/HDC	DUAL	1
151		io	line	l		IO_L15N/LDC0	DUAL	1
152		io	line	l		IO_L16P/LDC1	DUAL	1
153		io	line	l		IO_L16N/LDC2	DUAL	1
154		in	line	l		IP	INPUT	1
#

