# Symbol definition of Spartan-3E FPGA for gschem/gEDA
# Bank 2 (_2 deleted in pinlabel)
# S. Salewski, 26-OCT-2007
# File: XC3S500E-PQ208-B2.txt (based on file pq208_pinout.csv available from Xilinx)
# The Python script "tragesym" is used to convert this textual symbol definition into a symbol
# usage: tragesym XC3S500E-PQ208-B2.txt XC3S500E-PQ208-B2.sym

# tragesym options

[options]
# wordswap swaps labels if the pin is on the right side and looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=no
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=2400
pinwidthvertical=200
pinwidthhorizontal=400

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=XC3S500E-PQ208
device=XC3S500E-PQ208
refdes=U?
footprint=QFP208_28
description=FPGA
documentation=http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf
author=Stefan Salewski
dist-license=GPL
use-license=unlimited
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
comment=generated with Python script tragesym

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	comment
#-----------------------------------------------------
#pinnr	seq	type	style	posit	net 	label	type	bank		
#
54		in	line	l		IP	INPUT	2
55		io	line	l		IO_L01P/CSO_B	DUAL	2
56		io	line	l		IO_L01N/INIT_B	DUAL	2
57		in	line	l		IP_L02P	INPUT	2
58		in	line	l		IP_L02N	INPUT	2
60		io	line	l		IO_L03P/DOUT/BUSY	DUAL	2
61		io	line	l		IO_L03N/MOSI/CSI_B	DUAL	2
62		io	line	l		IO_L04P	I/O	2
63		io	line	l		IO_L04N	I/O	2
64		io	line	l		IO_L05P	I/O	2
65		io	line	l		IO_L05N	I/O	2
68		io	line	l		IO_L06P	I/O	2
69		io	line	l		IO_L06N	I/O	2
71		in	line	l		IP_L07P	INPUT	2
72		in	line	l		IP_L07N/VREF	VREF	2
74		io	line	l		IO_L08P/D7/GCLK12	DUAL/GCLK	2
75		io	line	l		IO_L08N/D6/GCLK13	DUAL/GCLK	2
76		io	line	l		IO/D5	DUAL	2
77		io	line	l		IO_L09P/D4/GCLK14	DUAL/GCLK	2
78		io	line	l		IO_L09N/D3/GCLK15	DUAL/GCLK	2
80		in	line	l		IP_L10P/RDWR_B/GCLK0	DUAL/GCLK	2
81		in	line	l		IP_L10N/M2/GCLK1	DUAL/GCLK	2
82		io	line	l		IO_L11P/D2/GCLK2	DUAL/GCLK	2
83		io	line	l		IO_L11N/D1/GCLK3	DUAL/GCLK	2
84		io	line	l		IO/M1	DUAL	2
86		io	line	l		IO_L12P/M0	DUAL	2
87		io	line	l		IO_L12N/DIN/D0	DUAL	2
89		io	line	l		IO_L13P	I/O	2
90		io	line	l		IO_L13N	I/O	2
91		in	line	l		IP	INPUT	2
93		io	line	l		IO_L14P/A23	DUAL	2
94		io	line	l		IO_L14N/A22	DUAL	2
96		io	line	l		IO_L15P/A21	DUAL	2
97		io	line	l		IO_L15N/A20	DUAL	2
98		io	line	l		IO/VREF	VREF	2
99		io	line	l		IO_L16P/VS2/A19	DUAL	2
100		io	line	l		IO_L16N/VS1/A18	DUAL	2
101		in	line	l		IP	INPUT	2
102		io	line	l		IO_L17P/VS0/A17	DUAL	2
103		io	line	l		IO_L17N/CCLK	DUAL	2
#

