# Symbol definition of Spartan-3E FPGA for gschem/gEDA
# Bank 3 (_3 deleted in pinlabel)
# S. Salewski, 26-OCT-2007
# File: XC3S500E-PQ208-B3.txt (based on file pq208_pinout.csv available from Xilinx)
# The Python script "tragesym" is used to convert this textual symbol definition into a symbol
# usage: tragesym XC3S500E-PQ208-B3.txt XC3S500E-PQ208-B3.sym

# tragesym options

[options]
# wordswap swaps labels if the pin is on the right side and looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=no
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=2400
pinwidthvertical=200
pinwidthhorizontal=400

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=XC3S500E-PQ208
device=XC3S500E-PQ208
refdes=U?
footprint=QFP208_28
description=FPGA
documentation=http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf
author=Stefan Salewski
dist-license=GPL
use-license=unlimited
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
comment=generated with Python script tragesym

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	comment
#-----------------------------------------------------
#pinnr	seq	type	style	posit	net 	label	type	bank		
#
2		io	line	l		IO_L01P	I/O	3
3		io	line	l		IO_L01N	I/O	3
4		io	line	l		IO_L02P	I/O	3
5		io	line	l		IO_L02N/VREF	VREF	3
6		in	line	l		IP	INPUT	3
8		io	line	l		IO_L03P	I/O	3
9		io	line	l		IO_L03N	I/O	3
11		io	line	l		IO_L04P	I/O	3
12		io	line	l		IO_L04N	I/O	3
14		in	line	l		IP	INPUT	3
15		io	line	l		IO_L05P	I/O	3
16		io	line	l		IO_L05N	I/O	3
18		io	line	l		IO_L06P	I/O	3
19		io	line	l		IO_L06N	I/O	3
20		in	line	l		IP/VREF	VREF	3
22		io	line	l		IO_L07P/LHCLK0	LHCLK	3
23		io	line	l		IO_L07N/LHCLK1	LHCLK	3
24		io	line	l		IO_L08P/LHCLK2	LHCLK	3
25		io	line	l		IO_L08N/LHCLK3/IRDY2	LHCLK	3
26		in	line	l		IP	INPUT	3
28		io	line	l		IO_L09P/LHCLK4/TRDY2	LHCLK	3
29		io	line	l		IO_L09N/LHCLK5	LHCLK	3
30		io	line	l		IO_L10P/LHCLK6	LHCLK	3
31		io	line	l		IO_L10N/LHCLK7	LHCLK	3
32		in	line	l		IP	INPUT	3
33		io	line	l		IO_L11P	I/O	3
34		io	line	l		IO_L11N	I/O	3
35		io	line	l		IO_L12P	I/O	3
36		io	line	l		IO_L12N	I/O	3
39		io	line	l		IO_L13P	I/O	3
40		io	line	l		IO_L13N	I/O	3
41		io	line	l		IO_L14P	I/O	3
42		io	line	l		IO_L14N	I/O	3
43		in	line	l		IP	INPUT	3
45		io	line	l		IO/VREF	VREF	3
47		io	line	l		IO_L15P	I/O	3
48		io	line	l		IO_L15N	I/O	3
49		io	line	l		IO_L16P	I/O	3
50		io	line	l		IO_L16N	I/O	3
51		in	line	l		IP	INPUT	3
#

