# Symbol definition of Spartan-3E FPGA for gschem/gEDA
# S. Salewski, 26-OCT-2007
# File: XC3S500E-PQ208.txt (based on file pq208_pinout.csv available from Xilinx)
# The Python script "tragesym" is used to convert this textual symbol definition into a symbol
# usage: tragesym XC3S500E-PQ208.txt XC3S500E-PQ208.sym
# This will result in a very large symbol with 208 pins --
# division in multiple subsymbols (power, bank0, bank1, bank2, bank3) is useful

# tragesym options

[options]
# wordswap swaps labels if the pin is on the right side and looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=no
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=2400
pinwidthvertical=200
pinwidthhorizontal=400

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=XC3S500E-PQ208
device=XC3S500E-PQ208
refdes=U?
footprint=QFP208_28
description=FPGA
documentation=http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf
author=Stefan Salewski
dist-license=GPL
use-license=unlimited
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
comment=generated with Python script tragesym

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	comment
#-----------------------------------------------------
#pinnr	seq	type	style	posit	net 	label	type	bank		
159		in	line	l		IP	INPUT	0
160		io	line	l		IO_L01P_0	I/O	0
161		io	line	l		IO_L01N_0	I/O	0
162		io	line	l		IO_L02P_0	I/O	0
163		io	line	l		IO_L02N_0/VREF_0	VREF	0
164		io	line	l		IO_L03P_0	I/O	0
165		io	line	l		IO_L03N_0	I/O	0
167		io	line	l		IO_L04P_0	I/O	0
168		io	line	l		IO_L04N_0/VREF_0	VREF	0
169		in	line	l		IP	INPUT	0
171		io	line	l		IO_L05P_0	I/O	0
172		io	line	l		IO_L05N_0	I/O	0
174		in	line	l		IP_L06P_0	INPUT	0
175		in	line	l		IP_L06N_0	INPUT	0
177		io	line	l		IO_L07P_0/GCLK4	GCLK	0
178		io	line	l		IO_L07N_0/GCLK5	GCLK	0
179		io	line	l		IO/VREF_0	VREF	0
180		io	line	l		IO_L08P_0/GCLK6	GCLK	0
181		io	line	l		IO_L08N_0/GCLK7	GCLK	0
183		in	line	l		IP_L09P_0/GCLK8	GCLK	0
184		in	line	l		IP_L09N_0/GCLK9	GCLK	0
185		io	line	l		IO_L10P_0/GCLK10	GCLK	0
186		io	line	l		IO_L10N_0/GCLK11	GCLK	0
187		io	line	l		IO	I/O	0
189		io	line	l		IO_L11P_0	I/O	0
190		io	line	l		IO_L11N_0	I/O	0
192		io	line	l		IO_L12P_0	I/O	0
193		io	line	l		IO_L12N_0/VREF_0	VREF	0
194		in	line	l		IP	INPUT	0
196		io	line	l		IO_L13P_0	I/O	0
197		io	line	l		IO_L13N_0	I/O	0
199		io	line	l		IO_L14P_0	I/O	0
200		io	line	l		IO_L14N_0/VREF_0	VREF	0
202		io	line	l		IO_L15P_0	I/O	0
203		io	line	l		IO_L15N_0	I/O	0
204		in	line	l		IP	INPUT	0
205		io	line	l		IO_L16P_0	I/O	0
206		io	line	l		IO_L16N_0/HSWAP	DUAL	0
#
106		io	line	l		IO_L01P_1/A16	DUAL	1
107		io	line	l		IO_L01N_1/A15	DUAL	1
108		io	line	l		IO_L02P_1/A14	DUAL	1
109		io	line	l		IO_L02N_1/A13	DUAL	1
110		in	line	l		IP	INPUT	1
112		io	line	l		IO_L03P_1	I/O	1
113		io	line	l		IO_L03N_1/VREF_1	VREF	1
115		io	line	l		IO_L04P_1	I/O	1
116		io	line	l		IO_L04N_1	I/O	1
118		in	line	l		IP	INPUT	1
119		io	line	l		IO_L05P_1/A12	DUAL	1
120		io	line	l		IO_L05N_1/A11	DUAL	1
122		io	line	l		IO_L06P_1	I/O	1
123		io	line	l		IO_L06N_1/VREF_1	VREF	1
124		in	line	l		IP	INPUT	1
126		io	line	l		IO_L07P_1/A10/RHCLK0	RHCLK/DUAL	1
127		io	line	l		IO_L07N_1/A9/RHCLK1	RHCLK/DUAL	1
128		io	line	l		IO_L08P_1/A8/RHCLK2	RHCLK/DUAL	1
129		io	line	l		IO_L08N_1/A7/RHCLK3/TRDY1	RHCLK/DUAL	1
130		in	line	l		IP	INPUT	1
132		io	line	l		IO_L09P_1/A6/RHCLK4/IRDY1	RHCLK/DUAL	1
133		io	line	l		IO_L09N_1/A5/RHCLK5	RHCLK/DUAL	1
134		io	line	l		IO_L10P_1/A4/RHCLK6	RHCLK/DUAL	1
135		io	line	l		IO_L10N_1/A3/RHCLK7	RHCLK/DUAL	1
136		in	line	l		IP/VREF_1	VREF	1
137		io	line	l		IO_L11P_1/A2	DUAL	1
138		io	line	l		IO_L11N_1/A1	DUAL	1
139		io	line	l		IO_L12P_1	I/O	1
140		io	line	l		IO_L12N_1/A0	DUAL	1
142		in	line	l		IP	INPUT	1
144		io	line	l		IO_L13P_1	I/O	1
145		io	line	l		IO_L13N_1	I/O	1
146		io	line	l		IO_L14P_1	I/O	1
147		io	line	l		IO_L14N_1	I/O	1
148		in	line	l		IP	INPUT	1
150		io	line	l		IO_L15P_1/HDC	DUAL	1
151		io	line	l		IO_L15N_1/LDC0	DUAL	1
152		io	line	l		IO_L16P_1/LDC1	DUAL	1
153		io	line	l		IO_L16N_1/LDC2	DUAL	1
154		in	line	l		IP	INPUT	1
#
54		in	line	l		IP	INPUT	2
55		io	line	l		IO_L01P_2/CSO_B	DUAL	2
56		io	line	l		IO_L01N_2/INIT_B	DUAL	2
57		in	line	l		IP_L02P_2	INPUT	2
58		in	line	l		IP_L02N_2	INPUT	2
60		io	line	l		IO_L03P_2/DOUT/BUSY	DUAL	2
61		io	line	l		IO_L03N_2/MOSI/CSI_B	DUAL	2
62		io	line	l		IO_L04P_2	I/O	2
63		io	line	l		IO_L04N_2	I/O	2
64		io	line	l		IO_L05P_2	I/O	2
65		io	line	l		IO_L05N_2	I/O	2
68		io	line	l		IO_L06P_2	I/O	2
69		io	line	l		IO_L06N_2	I/O	2
71		in	line	l		IP_L07P_2	INPUT	2
72		in	line	l		IP_L07N_2/VREF_2	VREF	2
74		io	line	l		IO_L08P_2/D7/GCLK12	DUAL/GCLK	2
75		io	line	l		IO_L08N_2/D6/GCLK13	DUAL/GCLK	2
76		io	line	l		IO/D5	DUAL	2
77		io	line	l		IO_L09P_2/D4/GCLK14	DUAL/GCLK	2
78		io	line	l		IO_L09N_2/D3/GCLK15	DUAL/GCLK	2
80		in	line	l		IP_L10P_2/RDWR_B/GCLK0	DUAL/GCLK	2
81		in	line	l		IP_L10N_2/M2/GCLK1	DUAL/GCLK	2
82		io	line	l		IO_L11P_2/D2/GCLK2	DUAL/GCLK	2
83		io	line	l		IO_L11N_2/D1/GCLK3	DUAL/GCLK	2
84		io	line	l		IO/M1	DUAL	2
86		io	line	l		IO_L12P_2/M0	DUAL	2
87		io	line	l		IO_L12N_2/DIN/D0	DUAL	2
89		io	line	l		IO_L13P_2	I/O	2
90		io	line	l		IO_L13N_2	I/O	2
91		in	line	l		IP	INPUT	2
93		io	line	l		IO_L14P_2/A23	DUAL	2
94		io	line	l		IO_L14N_2/A22	DUAL	2
96		io	line	l		IO_L15P_2/A21	DUAL	2
97		io	line	l		IO_L15N_2/A20	DUAL	2
98		io	line	l		IO/VREF_2	VREF	2
99		io	line	l		IO_L16P_2/VS2/A19	DUAL	2
100		io	line	l		IO_L16N_2/VS1/A18	DUAL	2
101		in	line	l		IP	INPUT	2
102		io	line	l		IO_L17P_2/VS0/A17	DUAL	2
103		io	line	l		IO_L17N_2/CCLK	DUAL	2
#
2		io	line	l		IO_L01P_3	I/O	3
3		io	line	l		IO_L01N_3	I/O	3
4		io	line	l		IO_L02P_3	I/O	3
5		io	line	l		IO_L02N_3/VREF_3	VREF	3
6		in	line	l		IP	INPUT	3
8		io	line	l		IO_L03P_3	I/O	3
9		io	line	l		IO_L03N_3	I/O	3
11		io	line	l		IO_L04P_3	I/O	3
12		io	line	l		IO_L04N_3	I/O	3
14		in	line	l		IP	INPUT	3
15		io	line	l		IO_L05P_3	I/O	3
16		io	line	l		IO_L05N_3	I/O	3
18		io	line	l		IO_L06P_3	I/O	3
19		io	line	l		IO_L06N_3	I/O	3
20		in	line	l		IP/VREF_3	VREF	3
22		io	line	l		IO_L07P_3/LHCLK0	LHCLK	3
23		io	line	l		IO_L07N_3/LHCLK1	LHCLK	3
24		io	line	l		IO_L08P_3/LHCLK2	LHCLK	3
25		io	line	l		IO_L08N_3/LHCLK3/IRDY2	LHCLK	3
26		in	line	l		IP	INPUT	3
28		io	line	l		IO_L09P_3/LHCLK4/TRDY2	LHCLK	3
29		io	line	l		IO_L09N_3/LHCLK5	LHCLK	3
30		io	line	l		IO_L10P_3/LHCLK6	LHCLK	3
31		io	line	l		IO_L10N_3/LHCLK7	LHCLK	3
32		in	line	l		IP	INPUT	3
33		io	line	l		IO_L11P_3	I/O	3
34		io	line	l		IO_L11N_3	I/O	3
35		io	line	l		IO_L12P_3	I/O	3
36		io	line	l		IO_L12N_3	I/O	3
39		io	line	l		IO_L13P_3	I/O	3
40		io	line	l		IO_L13N_3	I/O	3
41		io	line	l		IO_L14P_3	I/O	3
42		io	line	l		IO_L14N_3	I/O	3
43		in	line	l		IP	INPUT	3
45		io	line	l		IO/VREF_3	VREF	3
47		io	line	l		IO_L15P_3	I/O	3
48		io	line	l		IO_L15N_3	I/O	3
49		io	line	l		IO_L16P_3	I/O	3
50		io	line	l		IO_L16N_3	I/O	3
51		in	line	l		IP	INPUT	3
#
10		pwr	line	l		GND	GND	GND
17		pwr	line	l		GND	GND	GND
27		pwr	line	l		GND	GND	GND
37		pwr	line	l		GND	GND	GND
52		pwr	line	l		GND	GND	GND
53		pwr	line	l		GND	GND	GND
70		pwr	line	l		GND	GND	GND
79		pwr	line	l		GND	GND	GND
85		pwr	line	l		GND	GND	GND
95		pwr	line	l		GND	GND	GND
105		pwr	line	l		GND	GND	GND
121		pwr	line	l		GND	GND	GND
131		pwr	line	l		GND	GND	GND
141		pwr	line	l		GND	GND	GND
156		pwr	line	l		GND	GND	GND
173		pwr	line	l		GND	GND	GND
182		pwr	line	l		GND	GND	GND
188		pwr	line	l		GND	GND	GND
198		pwr	line	l		GND	GND	GND
208		pwr	line	l		GND	GND	GND
#
7		pwr	line	l		VCCAUX	VCCAUX	VCCAUX
44		pwr	line	l		VCCAUX	VCCAUX	VCCAUX
66		pwr	line	l		VCCAUX	VCCAUX	VCCAUX
92		pwr	line	l		VCCAUX	VCCAUX	VCCAUX
111		pwr	line	l		VCCAUX	VCCAUX	VCCAUX
149		pwr	line	l		VCCAUX	VCCAUX	VCCAUX
166		pwr	line	l		VCCAUX	VCCAUX	VCCAUX
195		pwr	line	l		VCCAUX	VCCAUX	VCCAUX
#
13		pwr	line	l		VCCINT	VCCINT	VCCINT
67		pwr	line	l		VCCINT	VCCINT	VCCINT
117		pwr	line	l		VCCINT	VCCINT	VCCINT
170		pwr	line	l		VCCINT	VCCINT	VCCINT
#
176		pwr	line	l		VCCO_0	VCCO	0
191		pwr	line	l		VCCO_0	VCCO	0
201		pwr	line	l		VCCO_0	VCCO	0
#
114		pwr	line	l		VCCO_1	VCCO	1
125		pwr	line	l		VCCO_1	VCCO	1
143		pwr	line	l		VCCO_1	VCCO	1
#
59		pwr	line	l		VCCO_2	VCCO	2
73		pwr	line	l		VCCO_2	VCCO	2
88		pwr	line	l		VCCO_2	VCCO	2
#
21		pwr	line	l		VCCO_3	VCCO	3
38		pwr	line	l		VCCO_3	VCCO	3
46		pwr	line	l		VCCO_3	VCCO	3
#
1		io	line	l		PROG_B	CONFIG	VCCAUX
104		io	line	l		DONE	CONFIG	VCCAUX
155		io	line	l		TMS	JTAG	VCCAUX
157		io	line	l		TDO	JTAG	VCCAUX
158		io	line	l		TCK	JTAG	VCCAUX
207		io	line	l		TDI	JTAG	VCCAUX

